Vivado on Yodalee Note

Vivado Best Practices in Automation

Sun, 31 May 2026 00:00:00 +0000

First of all, I don't know.

This is inherently a difficult topic. Vivado was not originally designed for automation (at least it doesn't seem like it). Its GUI and integrated Vivado project storage environment certainly provide a lot of functionality. However, in practice, it is strongly discouraged to include the entire Vivado generated project files into version control, as even slight changes can disrupt the version control system, making Vivado projects a pain point in automation and version management.

Using Xilinx Development Board: Connecting Interrupt

Fri, 15 May 2026 00:00:00 +0000

The story goes like this. Generally speaking, in the workflow of IP, we use AXI Lite to write into the register to instruct the IP to start working. So, how do we know when the IP has completed its work?

The simplest method is to map the IP status to a register and have the driver continuously harass ~~poll~~ this register. This technique is called busy polling — it's simple and crude, but the downside is that the driver gets stuck here and can't do anything else. Another method is that the IP issues an interrupt when it completes its task. Once the processor receives this interrupt, it signals the driver to handle the IP's post-processing tasks.

Using Xilinx Development Board: Connecting Writing DMA

Thu, 14 May 2026 00:00:00 +0000

In the previous chapter , we looked at how to read data from memory and provide it to the IP module. This time we will do the opposite, sending data from the IP module to memory. A lot of things are similar to reading, so we will skip much of the DMA-related introduction, making it somewhat simpler.

Test Module

We will implement a module that only streams data in one direction for writing. The implemented module is as follows:

Using Xilinx Development Board: Connect and Read DMA

Mon, 11 May 2026 00:00:00 +0000

In the previous article, we saw how to connect the AHB bus. In this article, let's take a look at AXI stream. If you have seen the usage of the AXI Lite interface, it helps convert AXI reading and writing into internal registers. However, each read and write is a time-consuming process. When there is a large amount of data that needs reading and writing, using AXI Lite and opening up hundreds of registers in the read and write space is very inefficient, making it difficult to efficiently send data to or from the IP.

Using Xilinx Development Board: Connecting AHB

Tue, 28 Apr 2026 00:00:00 +0000

In the previous article, we built a SoC on PynqZ2 and were able to control it using the AXI Lite interface. However, using AXI in reality is relatively luxurious; simpler implementations typically use simpler APB or AHB buses. In this article, we will explain how to implement and connect an AHB IP and allow the PS side to access it.

Packing AHB IP

Implementing a Readable and Writable AHB Module

The module we demonstrate is a simple AHB without any address. Any write will be stored in the register, and reading will return the bit-inverted result. In this era, this kind of module can just be written with the help of AI. Below is the prompt and its reply:

Using Xilinx Development Board: Connecting AXI Lite

Mon, 06 Apr 2026 00:00:00 +0000

The story goes like this, as previously mentioned my strong classmate gave me some articles related to Pynq AHB. Recently, after finishing a busy phase of work, I started revising the draft again and found that the article seemed a bit dry, so I decided to expand on it.