Verilog

Using VCS simulation in digital circuits

Here’s how the story goes: In the early days when I wrote verilog articles , and until recently when I wanted to do simple simulations, I was using iverilog as an example. However, it had the following two fatal flaws:

  1. Poor performance. I heard that since it transitioned to a compiled model in recent years, it has significantly accelerated, but I believe it’s still a notch slower compared to verilator and commercial software.
  2. Does not support SystemVerilog and VHDL. Writing pure Verilog these days is really painful, and using iverilog can’t simulate when implementing with SystemVerilog.
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