Verilog

In the previous discussion on Silicon IP , we briefly mentioned IEEE1735. However, I found that the principles of IEEE1735 could be explained more thoroughly, mainly by elucidating the effects IEEE1735 has on HDL files.

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Here's how the story goes: In the early days when I wrote verilog articles , and until recently when I wanted to do simple simulations, I was using iverilog as an example. However, it had the following two fatal flaws:

1. Poor performance. I heard that since it transitioned to a compiled model in recent years, it has significantly accelerated, but I believe it's still a notch slower compared to verilator and commercial software.
2. Does not support SystemVerilog and VHDL. Writing pure Verilog these days is really painful, and using iverilog can't simulate when implementing with SystemVerilog.

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I've finally reached my long-hidden ultimate goal. That's right, when I got this FPGA and was thinking about what to do, the answer I reached after a day was this: Nand2Tetris , actually building this CPU with FPGA. The previous UART, HDMI, BRAM were just appetizers, in fact, I am playing a very big game.
Of course, since we are using Verilog, we won't really start building up from NAND gates but instead implement with Verilog's built-in operations, so the parts in the first and second chapters of nand2tetris where NAND gates to logic gates and adders are made are skipped, and we start directly from the ALU.

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This update took a bit longer. The story goes like this: After testing HDMI, I spent some time trying to connect other devices with physical chips present on the FPGA board, including SDRAM, Flash, and SD card. The problem is that these aren't easy to connect, especially without an LA (Logic Analyzer), which makes it like a blind person feeling their way around. You can only use Verilator to simulate waveform; even if the waveform appears correct, if it doesn’t work when put into practice, you won't know what's wrong.

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Last time, we implemented UART input and output. This time, let's take on another interface included on the board: HDMI. With this implementation, we will have video output available. However, HDMI is a level more difficult than UART, so this time I directly modified the example code of icesugar-pro. For the TMDS part, I referred to an encoder available online.

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In the previous chapter, we mastered the open-source toolchain for FPGA. Next, we can test some of the interfaces of icesugar-pro. First, implementing an FPGA requires input and output, otherwise, it would just be a non-interactive program. The simplest input/output interface would be UART. A UART example is also provided on icesugar-pro's GitHub, where it continuously outputs "0" to "9" to your computer (note that there is a bug in this code XD). In this article, we will write a UART module with tx and rx.

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The story goes like this, this year's COSCUP submitted a session on System Software. The session track host independently offered a submission reward, originally posted on Facebook:

To encourage students to submit and to experience the value of knowledge, after discussing with Mr. Jserv, we will provide two paid manuscript solicitation spots to the students here.
The first two students whose submissions are accepted will receive a reward of 2,500 NTD and an FPGA development board with a RISC-V core capable of running Linux!

I declined the monetary reward. Ethically it wouldn't be right for a salaried person to take this money, so it's better left to student speakers more talented than me.
However, I accepted the FPGA, after evaluating since it's hard to find. Previously our lab's DE2 was priced over ten thousand NTD (and it's discontinued now), and some projects without hardware lack a certain feel. I had always wanted an FPGA to play with, so I accepted the FPGA.

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