ICdesign

In modern chip design, as chip functions become increasingly complex and the number of logic gates easily reaches billions, ensuring the chip can operate correctly post-manufacture has become a major challenging issue. Despite efforts from EDA software like Design Compiler and INNOVUS ensuring timing correctness in the design, process variations can also lead to chip defects. Therefore, we need an effective method to thoroughly test the chip’s internals before it hits the market. That’s where Design for Testability (DFT) comes into play.

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In the previous article, we looked at the use of Design Compiler to synthesize our circuits into logic gates. The next steps are to either send it for LEC or do a post-synthesis simulation, after which we will proceed to the main task of using APR to draw the Layout. Before APR, let’s take a single article to see what needs to be prepared before APR.

Be aware that the instructions here are for Cadence’s INNOVUS, and some content is likely different from Synopsys ICC2. If you are an ICC2 user, please be cautious when referencing.

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Here’s how the story goes: In the early days when I wrote verilog articles , and until recently when I wanted to do simple simulations, I was using iverilog as an example. However, it had the following two fatal flaws:

1. Poor performance. I heard that since it transitioned to a compiled model in recent years, it has significantly accelerated, but I believe it’s still a notch slower compared to verilator and commercial software.
2. Does not support SystemVerilog and VHDL. Writing pure Verilog these days is really painful, and using iverilog can’t simulate when implementing with SystemVerilog.

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After discussing design constraint, this article introduces the leading tool for chip synthesis during tape-out - Synopsys Design Compiler.

To be honest, I was a bit hesitant to write this article, because as the leading tool, Design Compiler doesn’t really need my introduction. Cadence also has a corresponding tape-out tool called Genus, but… I only know how to use Design Compiler. If Cadence were to sponsor me for a course, I’d be willing to write an article for them (wink).

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After writing Verilog, we move on to a somewhat complex topic, which is discussing what circuit synthesis does. If we use software as a metaphor, what synthesis does is similar to a software compiler. Software is written in a high-level language and then converted into Assembly and machine code through the compiler. In hardware, high-level languages like VHDL/Verilog are used (yes, they are considered high-level languages), and through a synthesis tool, they are converted into gate-level designs. Unless you’re researching standard libraries, not many people write their own adders and multipliers.

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Before talking about APR, let’s first discuss the physical architecture inside a chip, such as pad, bond wire, memory, power ring, power strip, etc., so that everyone can have an understanding of the chip they commonly see, making it easier to write articles with practical software operations later.

This article has been modified extensively after completion, with both the text and images updated significantly to correct any erroneous content. If you are interested in the history of the article, you can search for the history record of the article on Github.

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Following up on our previous introduction , today we will first look at an overview of the tape-out process. The goal of this article is to provide everyone with a basic understanding of the tape-out process, so that the subsequent articles will be easier to understand. Originally, the plan was to quickly publish this article after finishing the introduction, but I decided to wait until the chip taped out in November returns and I confirm that the tape-out successfully meets the initial design before continuing with the subsequent articles. This way, I can speak with more confidence… Yes, it has to be that reason, and definitely not because I’ve been goofing off after work every day.

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The story goes like this: Recently, after many years, I delved back into digital circuit design and tapeout, a field I had been distant from for quite a while. On November 13th, with the pressure on, I submitted my first ever digital circuit chip. I’m writing this preface to document future related posts.

The last time I dabbled in digital circuit design was during my university days, even before I started this blog, which shows how long ago it was. I wanted to write this article because I found very few related records and articles online during this tapeout process. The articles I did find were either in Simplified Chinese or English. The only detailed Traditional Chinese one I found was HaoYu’s Notes . Besides that, I had to rely on my college classmates for help. Sending out this tapeout on 11/13 was largely thanks to their tremendous support, including long-term partner JJL and phoning, whose support I’ve relied heavily upon from university through graduate school to now.

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