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Before talking about APR, let's first discuss the physical architecture inside a chip, such as pad, bond wire, memory, power ring, power strip, etc., so that everyone can have an understanding of the chip they commonly see, making it easier to write articles with practical software operations later.

This article has been modified extensively after completion, with both the text and images updated significantly to correct any erroneous content. If you are interested in the history of the article, you can search for the history record of the article on Github.

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Following up on our previous introduction , today we will first look at an overview of the tape-out process. The goal of this article is to provide everyone with a basic understanding of the tape-out process, so that the subsequent articles will be easier to understand. Originally, the plan was to quickly publish this article after finishing the introduction, but I decided to wait until the chip taped out in November returns and I confirm that the tape-out successfully meets the initial design before continuing with the subsequent articles. This way, I can speak with more confidence... Yes, it has to be that reason, and definitely not because I've been goofing off after work every day.

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The story goes like this: Recently, after many years, I delved back into digital circuit design and tapeout, a field I had been distant from for quite a while. On November 13th, with the pressure on, I submitted my first ever digital circuit chip. I'm writing this preface to document future related posts.

The last time I dabbled in digital circuit design was during my university days, even before I started this blog, which shows how long ago it was. I wanted to write this article because I found very few related records and articles online during this tapeout process. The articles I did find were either in Simplified Chinese or English. The only detailed Traditional Chinese one I found was HaoYu's Notes . Besides that, I had to rely on my college classmates for help. Sending out this tapeout on 11/13 was largely thanks to their tremendous support, including long-term partner JJL and phoning, whose support I've relied heavily upon from university through graduate school to now.

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The story goes like this: about a year and a half ago, I spent a few months playing around with the FPGA I got from COSCUP. At that time, I was developing on my desktop, which runs Archlinux. Recently, for some reasons, I took out this board again, but this time, I switched to my new laptop, which is installed with Windows WSL and Ubuntu 22.04, and discovered that among the tools I listed in the article , including yosys, nextpnr, prjtrellis, only yosys could be installed using apt on Ubuntu, while the others had to be compiled manually, unlike on Archlinux where someone has already set up AUR for you.

This article is a note on installing tools, hoping to help others who want to play with Lattice FPGA on Ubuntu. It primarily references this article , as well as some issues from the tools' Github.

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I've finally reached my long-hidden ultimate goal. That's right, when I got this FPGA and was thinking about what to do, the answer I reached after a day was this: Nand2Tetris , actually building this CPU with FPGA. The previous UART, HDMI, BRAM were just appetizers, in fact, I am playing a very big game.
Of course, since we are using Verilog, we won't really start building up from NAND gates but instead implement with Verilog's built-in operations, so the parts in the first and second chapters of nand2tetris where NAND gates to logic gates and adders are made are skipped, and we start directly from the ALU.

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This update took a bit longer. The story goes like this: After testing HDMI, I spent some time trying to connect other devices with physical chips present on the FPGA board, including SDRAM, Flash, and SD card. The problem is that these aren't easy to connect, especially without an LA (Logic Analyzer), which makes it like a blind person feeling their way around. You can only use Verilator to simulate waveform; even if the waveform appears correct, if it doesn’t work when put into practice, you won't know what's wrong.

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Last time, we implemented UART input and output. This time, let's take on another interface included on the board: HDMI. With this implementation, we will have video output available. However, HDMI is a level more difficult than UART, so this time I directly modified the example code of icesugar-pro. For the TMDS part, I referred to an encoder available online.

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In the previous chapter, we mastered the open-source toolchain for FPGA. Next, we can test some of the interfaces of icesugar-pro. First, implementing an FPGA requires input and output, otherwise, it would just be a non-interactive program. The simplest input/output interface would be UART. A UART example is also provided on icesugar-pro's GitHub, where it continuously outputs "0" to "9" to your computer (note that there is a bug in this code XD). In this article, we will write a UART module with tx and rx.

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The story goes like this, this year's COSCUP submitted a session on System Software. The session track host independently offered a submission reward, originally posted on Facebook:

To encourage students to submit and to experience the value of knowledge, after discussing with Mr. Jserv, we will provide two paid manuscript solicitation spots to the students here.
The first two students whose submissions are accepted will receive a reward of 2,500 NTD and an FPGA development board with a RISC-V core capable of running Linux!

I declined the monetary reward. Ethically it wouldn't be right for a salaried person to take this money, so it's better left to student speakers more talented than me.
However, I accepted the FPGA, after evaluating since it's hard to find. Previously our lab's DE2 was priced over ten thousand NTD (and it's discontinued now), and some projects without hardware lack a certain feel. I had always wanted an FPGA to play with, so I accepted the FPGA.

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