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In the previous discussion on Silicon IP , we briefly mentioned IEEE1735. However, I found that the principles of IEEE1735 could be explained more thoroughly, mainly by elucidating the effects IEEE1735 has on HDL files.

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When you are in the Warring States period, traveling around the various states is a necessary skill.

In the previous articles on design constraint and design compiler , it was mentioned that each path in a chip is checked to ensure that the delay between each set of registers meets the Timing Constraint. This check is crucial because if the Timing Constraint is not met, the chip can only operate at a downgraded specification.

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This article is similar to the previous DFT, introducing ECO, something I haven't fully tried yet, and how we support ECO in design, along with the most commonly used ECO solution in layout, Spare Cell.

When your chip reaches product level, you may need to consider ECO issues. ECO stands for Engineering Change Order, and you can refer to the following article for more information: What is ECO in Chip Design? . If I had to summarize it in one word, ECO is the process of discovering design problems, where formal procedures have been completed and there is no time to use the formal approach within the schedule, so engineering methods are used to forcibly resolve the issue, like the example of the building in New York that was found to be potentially unstable and reinforced with steel plates to ensure safety.

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The story goes like this: Recently, I took on a project at the company where the process used only 3 metal layers, which is vastly different from previous ones I've worked on, such as .18 microns with 5 metal layers, 90 nm with 9 metal layers, and 40 nm with 10 layers (strictly speaking, only nine layers). This caused a lot of issues with innovus layout, and it's worth writing an article to thoroughly document the experience.

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The story goes like this: In the massive hardware industry, no single company can independently create a chip. Even Tier-1 companies like Nvidia and AMD have many designs that come from licensed IP (Intellectual Property). Modern chips are like building blocks of IP, where each block may represent the hard work and dedication of countless engineers, along with the substantial investment in verification and optimization.

If you want to license your design to others, you certainly can't just offer up the RTL code for free. Otherwise, the buyer could directly look at your code, understand the concept, and implement it themselves. Protecting hardware intellectual property rights is so important that IEEE even has a standard IEEE 1735 to address this issue. All major EDA (Electronic Design Automation) vendors have tools that support IEEE 1735; the latest version is the second edition, released in 2023.

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In modern chip design, as chip functions become increasingly complex and the number of logic gates easily reaches billions, ensuring the chip can operate correctly post-manufacture has become a major challenging issue. Despite efforts from EDA software like Design Compiler and INNOVUS ensuring timing correctness in the design, process variations can also lead to chip defects. Therefore, we need an effective method to thoroughly test the chip’s internals before it hits the market. That's where Design for Testability (DFT) comes into play.

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In the previous article, we looked at the use of Design Compiler to synthesize our circuits into logic gates. The next steps are to either send it for LEC or do a post-synthesis simulation, after which we will proceed to the main task of using APR to draw the Layout. Before APR, let's take a single article to see what needs to be prepared before APR.

Be aware that the instructions here are for Cadence's INNOVUS, and some content is likely different from Synopsys ICC2. If you are an ICC2 user, please be cautious when referencing.

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Here's how the story goes: In the early days when I wrote verilog articles , and until recently when I wanted to do simple simulations, I was using iverilog as an example. However, it had the following two fatal flaws:

1. Poor performance. I heard that since it transitioned to a compiled model in recent years, it has significantly accelerated, but I believe it's still a notch slower compared to verilator and commercial software.
2. Does not support SystemVerilog and VHDL. Writing pure Verilog these days is really painful, and using iverilog can't simulate when implementing with SystemVerilog.

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After discussing design constraint, this article introduces the leading tool for chip synthesis during tape-out - Synopsys Design Compiler.

To be honest, I was a bit hesitant to write this article, because as the leading tool, Design Compiler doesn't really need my introduction. Cadence also has a corresponding tape-out tool called Genus, but... I only know how to use Design Compiler. If Cadence were to sponsor me for a course, I'd be willing to write an article for them (wink).

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After writing Verilog, we move on to a somewhat complex topic, which is discussing what circuit synthesis does. If we use software as a metaphor, what synthesis does is similar to a software compiler. Software is written in a high-level language and then converted into Assembly and machine code through the compiler. In hardware, high-level languages like VHDL/Verilog are used (yes, they are considered high-level languages), and through a synthesis tool, they are converted into gate-level designs. Unless you're researching standard libraries, not many people write their own adders and multipliers.

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