The story goes like this: whether it's digital, analog, or microwave circuits, the final step for a chip is to undergo what's called the signoff process, which includes the final inspection to check if there are any design issues, among other things.
...When going online and offline, the parts that require time to operate are mainly floorplan and powerplan. Once placement has started, it's about pressing a button and then watching animations, coming back after watching a segment to see if it's finished.
For example, during a recent offline session, I watched the entire season of MYGO . During the previous 1P3M , I watched the entire season of Frieren.
Overall, the steps here are repeated as follows:
...Finally entered Power Plan, this part is like wiring your house, from the power supply pad all the way to the lowest level standard cell. You need to complete Power Ring, Macro Ring, Power Stripe, and Follow Pin.
Generally, the Power Pad will supply power from layers M1-M3, so the Power Ring usually stops at M4 or M5 to avoid blocking the lines coming from the Pad. I generally choose a width of 3-4 um for the Power Ring, depending on the power consumption and number of Wire Groups of the chip. The metal process has a density limit, generally between 30% - 70%. The width of the gap in the Power Ring is set to half the line width. This gives an overall metal density of 66%, which is just within the upper limit of the density check of 70%.
...After preparing the offline materials, this article starts operating INNOVUS for layout. In fact, I was really uncertain about what to write because I don't have INNOVUS available at hand, and without screenshot images (unless I steal them), talking only about procedures feels like a manual. Therefore, this article was left unwritten for a while.
In the end, I still wrote it, adding some personal experiences and terminology explanations along with the steps. Because the article ended up being quite long, I've split it into three parts: Floorplan, Powerplan, and P&R.
...First of all, I don't know.
This is inherently a difficult topic. Vivado was not originally designed for automation (at least it doesn't seem like it). Its GUI and integrated Vivado project storage environment certainly provide a lot of functionality. However, in practice, it is strongly discouraged to include the entire Vivado generated project files into version control, as even slight changes can disrupt the version control system, making Vivado projects a pain point in automation and version management.
...The story goes like this. Generally speaking, in the workflow of IP, we use AXI Lite to write into the register to instruct the IP to start working. So, how do we know when the IP has completed its work?
The simplest method is to map the IP status to a register and have the driver continuously harass poll this register. This technique is called busy polling — it's simple and crude, but the downside is that the driver gets stuck here and can't do anything else.
Another method is that the IP issues an interrupt when it completes its task. Once the processor receives this interrupt, it signals the driver to handle the IP's post-processing tasks.
In the previous chapter , we looked at how to read data from memory and provide it to the IP module. This time we will do the opposite, sending data from the IP module to memory. A lot of things are similar to reading, so we will skip much of the DMA-related introduction, making it somewhat simpler.
We will implement a module that only streams data in one direction for writing. The implemented module is as follows:
...In the previous article, we saw how to connect the AHB bus. In this article, let's take a look at AXI stream. If you have seen the usage of the AXI Lite interface, it helps convert AXI reading and writing into internal registers. However, each read and write is a time-consuming process. When there is a large amount of data that needs reading and writing, using AXI Lite and opening up hundreds of registers in the read and write space is very inefficient, making it difficult to efficiently send data to or from the IP.
...In the previous article, we built a SoC on PynqZ2 and were able to control it using the AXI Lite interface. However, using AXI in reality is relatively luxurious; simpler implementations typically use simpler APB or AHB buses. In this article, we will explain how to implement and connect an AHB IP and allow the PS side to access it.
The module we demonstrate is a simple AHB without any address. Any write will be stored in the register, and reading will return the bit-inverted result. In this era, this kind of module can just be written with the help of AI. Below is the prompt and its reply:
...The story goes like this, as previously mentioned my strong classmate gave me some articles related to Pynq AHB. Recently, after finishing a busy phase of work, I started revising the draft again and found that the article seemed a bit dry, so I decided to expand on it.
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