The story goes like this. Generally speaking, in the workflow of IP, we use AXI Lite to write into the register to instruct the IP to start working. So, how do we know when the IP has completed its work?

The simplest method is to map the IP status to a register and have the driver continuously harass poll this register. This technique is called busy polling — it's simple and crude, but the downside is that the driver gets stuck here and can't do anything else. Another method is that the IP issues an interrupt when it completes its task. Once the processor receives this interrupt, it signals the driver to handle the IP's post-processing tasks.

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In the previous chapter , we looked at how to read data from memory and provide it to the IP module. This time we will do the opposite, sending data from the IP module to memory. A lot of things are similar to reading, so we will skip much of the DMA-related introduction, making it somewhat simpler.

Test Module

We will implement a module that only streams data in one direction for writing. The implemented module is as follows:

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In the previous article, we saw how to connect the AHB bus. In this article, let's take a look at AXI stream. If you have seen the usage of the AXI Lite interface, it helps convert AXI reading and writing into internal registers. However, each read and write is a time-consuming process. When there is a large amount of data that needs reading and writing, using AXI Lite and opening up hundreds of registers in the read and write space is very inefficient, making it difficult to efficiently send data to or from the IP.

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In the previous article, we built a SoC on PynqZ2 and were able to control it using the AXI Lite interface. However, using AXI in reality is relatively luxurious; simpler implementations typically use simpler APB or AHB buses. In this article, we will explain how to implement and connect an AHB IP and allow the PS side to access it.

Packing AHB IP

Implementing a Readable and Writable AHB Module

The module we demonstrate is a simple AHB without any address. Any write will be stored in the register, and reading will return the bit-inverted result. In this era, this kind of module can just be written with the help of AI. Below is the prompt and its reply:

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The story goes like this, as previously mentioned my strong classmate gave me some articles related to Pynq AHB. Recently, after finishing a busy phase of work, I started revising the draft again and found that the article seemed a bit dry, so I decided to expand on it.

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The story goes like this: about a year and a half ago, I spent a few months playing around with the FPGA I got from COSCUP. At that time, I was developing on my desktop, which runs Archlinux. Recently, for some reasons, I took out this board again, but this time, I switched to my new laptop, which is installed with Windows WSL and Ubuntu 22.04, and discovered that among the tools I listed in the article , including yosys, nextpnr, prjtrellis, only yosys could be installed using apt on Ubuntu, while the others had to be compiled manually, unlike on Archlinux where someone has already set up AUR for you.

This article is a note on installing tools, hoping to help others who want to play with Lattice FPGA on Ubuntu. It primarily references this article , as well as some issues from the tools' Github.

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I've finally reached my long-hidden ultimate goal. That's right, when I got this FPGA and was thinking about what to do, the answer I reached after a day was this: Nand2Tetris , actually building this CPU with FPGA. The previous UART, HDMI, BRAM were just appetizers, in fact, I am playing a very big game.
Of course, since we are using Verilog, we won't really start building up from NAND gates but instead implement with Verilog's built-in operations, so the parts in the first and second chapters of nand2tetris where NAND gates to logic gates and adders are made are skipped, and we start directly from the ALU.

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This update took a bit longer. The story goes like this: After testing HDMI, I spent some time trying to connect other devices with physical chips present on the FPGA board, including SDRAM, Flash, and SD card. The problem is that these aren't easy to connect, especially without an LA (Logic Analyzer), which makes it like a blind person feeling their way around. You can only use Verilator to simulate waveform; even if the waveform appears correct, if it doesn’t work when put into practice, you won't know what's wrong.

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Last time, we implemented UART input and output. This time, let's take on another interface included on the board: HDMI. With this implementation, we will have video output available. However, HDMI is a level more difficult than UART, so this time I directly modified the example code of icesugar-pro. For the TMDS part, I referred to an encoder available online.

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In the previous chapter, we mastered the open-source toolchain for FPGA. Next, we can test some of the interfaces of icesugar-pro. First, implementing an FPGA requires input and output, otherwise, it would just be a non-interactive program. The simplest input/output interface would be UART. A UART example is also provided on icesugar-pro's GitHub, where it continuously outputs "0" to "9" to your computer (note that there is a bug in this code XD). In this article, we will write a UART module with tx and rx.

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