The story goes like this: whether it's digital, analog, or microwave circuits, the final step for a chip is to undergo what's called the signoff process, which includes the final inspection to check if there are any design issues, among other things.
...When going online and offline, the parts that require time to operate are mainly floorplan and powerplan. Once placement has started, it's about pressing a button and then watching animations, coming back after watching a segment to see if it's finished.
For example, during a recent offline session, I watched the entire season of MYGO . During the previous 1P3M , I watched the entire season of Frieren.
Overall, the steps here are repeated as follows:
...Finally entered Power Plan, this part is like wiring your house, from the power supply pad all the way to the lowest level standard cell. You need to complete Power Ring, Macro Ring, Power Stripe, and Follow Pin.
Generally, the Power Pad will supply power from layers M1-M3, so the Power Ring usually stops at M4 or M5 to avoid blocking the lines coming from the Pad. I generally choose a width of 3-4 um for the Power Ring, depending on the power consumption and number of Wire Groups of the chip. The metal process has a density limit, generally between 30% - 70%. The width of the gap in the Power Ring is set to half the line width. This gives an overall metal density of 66%, which is just within the upper limit of the density check of 70%.
...After preparing the offline materials, this article starts operating INNOVUS for layout. In fact, I was really uncertain about what to write because I don't have INNOVUS available at hand, and without screenshot images (unless I steal them), talking only about procedures feels like a manual. Therefore, this article was left unwritten for a while.
In the end, I still wrote it, adding some personal experiences and terminology explanations along with the steps. Because the article ended up being quite long, I've split it into three parts: Floorplan, Powerplan, and P&R.
...When you are in the Warring States period, traveling around the various states is a necessary skill.
In the previous articles on design constraint and design compiler , it was mentioned that each path in a chip is checked to ensure that the delay between each set of registers meets the Timing Constraint. This check is crucial because if the Timing Constraint is not met, the chip can only operate at a downgraded specification.
...This article is similar to the previous DFT, introducing ECO, something I haven't fully tried yet, and how we support ECO in design, along with the most commonly used ECO solution in layout, Spare Cell.
When your chip reaches product level, you may need to consider ECO issues. ECO stands for Engineering Change Order, and you can refer to the following article for more information: What is ECO in Chip Design? . If I had to summarize it in one word, ECO is the process of discovering design problems, where formal procedures have been completed and there is no time to use the formal approach within the schedule, so engineering methods are used to forcibly resolve the issue, like the example of the building in New York that was found to be potentially unstable and reinforced with steel plates to ensure safety.
...The story goes like this: Recently, I took on a project at the company where the process used only 3 metal layers, which is vastly different from previous ones I've worked on, such as .18 microns with 5 metal layers, 90 nm with 9 metal layers, and 40 nm with 10 layers (strictly speaking, only nine layers). This caused a lot of issues with innovus layout, and it's worth writing an article to thoroughly document the experience.
...The story goes like this: In the massive hardware industry, no single company can independently create a chip. Even Tier-1 companies like Nvidia and AMD have many designs that come from licensed IP (Intellectual Property). Modern chips are like building blocks of IP, where each block may represent the hard work and dedication of countless engineers, along with the substantial investment in verification and optimization.
If you want to license your design to others, you certainly can't just offer up the RTL code for free. Otherwise, the buyer could directly look at your code, understand the concept, and implement it themselves. Protecting hardware intellectual property rights is so important that IEEE even has a standard IEEE 1735 to address this issue. All major EDA (Electronic Design Automation) vendors have tools that support IEEE 1735; the latest version is the second edition, released in 2023.
...In modern chip design, as chip functions become increasingly complex and the number of logic gates easily reaches billions, ensuring the chip can operate correctly post-manufacture has become a major challenging issue. Despite efforts from EDA software like Design Compiler and INNOVUS ensuring timing correctness in the design, process variations can also lead to chip defects. Therefore, we need an effective method to thoroughly test the chip’s internals before it hits the market. That's where Design for Testability (DFT) comes into play.
...In the previous article, we looked at the use of Design Compiler to synthesize our circuits into logic gates. The next steps are to either send it for LEC or do a post-synthesis simulation, after which we will proceed to the main task of using APR to draw the Layout. Before APR, let's take a single article to see what needs to be prepared before APR.
Be aware that the instructions here are for Cadence's INNOVUS, and some content is likely different from Synopsys ICC2. If you are an ICC2 user, please be cautious when referencing.
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