The story goes like this: whether it's digital, analog, or microwave circuits, the final step for a chip is to undergo what's called the signoff process, which includes the final inspection to check if there are any design issues, among other things.
...When going online and offline, the parts that require time to operate are mainly floorplan and powerplan. Once placement has started, it's about pressing a button and then watching animations, coming back after watching a segment to see if it's finished.
For example, during a recent offline session, I watched the entire season of MYGO . During the previous 1P3M , I watched the entire season of Frieren.
Overall, the steps here are repeated as follows:
...Finally entered Power Plan, this part is like wiring your house, from the power supply pad all the way to the lowest level standard cell. You need to complete Power Ring, Macro Ring, Power Stripe, and Follow Pin.
Generally, the Power Pad will supply power from layers M1-M3, so the Power Ring usually stops at M4 or M5 to avoid blocking the lines coming from the Pad. I generally choose a width of 3-4 um for the Power Ring, depending on the power consumption and number of Wire Groups of the chip. The metal process has a density limit, generally between 30% - 70%. The width of the gap in the Power Ring is set to half the line width. This gives an overall metal density of 66%, which is just within the upper limit of the density check of 70%.
...After preparing the offline materials, this article starts operating INNOVUS for layout. In fact, I was really uncertain about what to write because I don't have INNOVUS available at hand, and without screenshot images (unless I steal them), talking only about procedures feels like a manual. Therefore, this article was left unwritten for a while.
In the end, I still wrote it, adding some personal experiences and terminology explanations along with the steps. Because the article ended up being quite long, I've split it into three parts: Floorplan, Powerplan, and P&R.
...In modern chip design, as chip functions become increasingly complex and the number of logic gates easily reaches billions, ensuring the chip can operate correctly post-manufacture has become a major challenging issue. Despite efforts from EDA software like Design Compiler and INNOVUS ensuring timing correctness in the design, process variations can also lead to chip defects. Therefore, we need an effective method to thoroughly test the chip’s internals before it hits the market. That's where Design for Testability (DFT) comes into play.
...In the previous article, we looked at the use of Design Compiler to synthesize our circuits into logic gates. The next steps are to either send it for LEC or do a post-synthesis simulation, after which we will proceed to the main task of using APR to draw the Layout. Before APR, let's take a single article to see what needs to be prepared before APR.
Be aware that the instructions here are for Cadence's INNOVUS, and some content is likely different from Synopsys ICC2. If you are an ICC2 user, please be cautious when referencing.
...After discussing design constraint, this article introduces the leading tool for chip synthesis during tape-out - Synopsys Design Compiler.
To be honest, I was a bit hesitant to write this article, because as the leading tool, Design Compiler doesn't really need my introduction. Cadence also has a corresponding tape-out tool called Genus, but... I only know how to use Design Compiler. If Cadence were to sponsor me for a course, I'd be willing to write an article for them (wink).
...After writing Verilog, we move on to a somewhat complex topic, which is discussing what circuit synthesis does. If we use software as a metaphor, what synthesis does is similar to a software compiler. Software is written in a high-level language and then converted into Assembly and machine code through the compiler. In hardware, high-level languages like VHDL/Verilog are used (yes, they are considered high-level languages), and through a synthesis tool, they are converted into gate-level designs. Unless you're researching standard libraries, not many people write their own adders and multipliers.
...Before talking about APR, let's first discuss the physical architecture inside a chip, such as pad, bond wire, memory, power ring, power strip, etc., so that everyone can have an understanding of the chip they commonly see, making it easier to write articles with practical software operations later.
This article has been modified extensively after completion, with both the text and images updated significantly to correct any erroneous content. If you are interested in the history of the article, you can search for the history record of the article on Github.
...Following up on our previous introduction , today we will first look at an overview of the tape-out process. The goal of this article is to provide everyone with a basic understanding of the tape-out process, so that the subsequent articles will be easier to understand. Originally, the plan was to quickly publish this article after finishing the introduction, but I decided to wait until the chip taped out in November returns and I confirm that the tape-out successfully meets the initial design before continuing with the subsequent articles. This way, I can speak with more confidence... Yes, it has to be that reason, and definitely not because I've been goofing off after work every day.
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